High-frequency circuit block, its manufacturing method, high-frequency module device, and its manufacturing method

ABSTRACT

A high frequency module device having a high frequency circuit block unit including a passive device. A plural number of unit wiring layers, each formed by an insulating layer, having a passive device unit in its portion, and by a pattern wiring, are layered on a dummy substrate, and are released from the dummy substrate to form the high frequency circuit block unit ( 2 ), which is mounted on a motherboard ( 3 ). The major surfaces of the respective unit wiring layers are planarized. The passive device unit and the pattern wiring, formed on the major surface of each unit wiring layer in the high frequency circuit block unit ( 2 ), can be formed with high accuracy to improve high frequency characteristics. The high frequency circuit block unit ( 2 ) is not in need of a base substrate, thus achieves reduction in size and cost.

TECHNICAL FIELD

[0001] This invention relates to a high frequency circuit block unit,having a passive device, a manufacturing method therefor, a highfrequency module device having the high frequency circuit block unitmounted on a motherboard, and a manufacturing method therefor.

[0002] This application claims priority of Japanese Patent ApplicationNo.2001-359853, filed on Nov. 26, 2001, the entirety of which isincorporated by reference herein.

BACKGROUND ART

[0003] A variety of the information, such as audio or video information,is converted into digital signals and handled as digital data, and hencemay readily be handled by for example a personal computer or by a mobilecomputer. The above information may be compressed in bandwidth by anaudio codec or video codec technology so as to be distributed by digitalcommunication or digital broadcast to a variety of communicationterminal equipment readily efficiently. For example, audio/video data(AV data) may be received outdoors by portable telephone sets.

[0004] The transmitting/receiving system for e.g., AV data has come tobe variably used through the proposal of a network system usable in asmall local area, including households. As the network system, thenext-generation wireless radio communication systems of the 5 GHz rangeas proposed for example in IEEE 802.11a, wireless radio LAN system ofthe 2.45 GHz range as proposed for example in IEEE 802.11b or in thenear-distance wireless communication system, termed Bluetooth, is nowstirring up notice.

[0005] The transmitting/receiving system for e.g., data exploits thewireless network system effectively to enable exchange of variable data,access to the Internet or transmission/reception of data in variablelocations, such as in households or outdoors, conveniently without theinterposition of relaying devices.

[0006] In a transmitting/receiving system for e.g., data, development ofa communication terminal equipment which is small-sized, lightweight andportable and which has the above-mentioned communication functions, isessential. In communication terminal equipment, high frequency analogsignals need to be modulated/demodulated in the transmission/receptionsection. Thus, there is usually provided a high frequencytransmission/reception circuit 100 by the superheterodyne system inwhich transmission/reception signals are once converted from thetransmission/reception signals into signals of the intermediatefrequency, as shown in FIG. 1.

[0007] The high frequency transmission/reception circuit 100 includes anantenna unit 101 having an antenna or a changeover switch for receivingor transmitting information signals and a transmission/receptionswitching unit 102 for switching between transmission and reception. Thehigh frequency transmission/reception circuit 100 also includes areception circuit unit 105 made up by a frequency conversion circuitsection 103 and a demodulating circuit section 104. The high frequencytransmission/reception circuit 100 includes a transmission circuit unit109 made up by a power amplifier 106, a drive amplifier 107 and amodulating circuit section 108. The high frequencytransmission/reception circuit 100 also includes a reference frequencygenerating circuit unit for supplying the reference frequency to thereception circuit unit 105 and to the transmission circuit unit 109.

[0008] The above-described high frequency transmission/reception circuit100 is made up by an extremely large number of component parts, notshown in detail. These include large-sized functional parts, such asfilters introduced between different stages, a local oscillator (voltagecontrolled oscillator or VOC), a SAW (surface acoustic wave) filter andpassive component parts, such as inductance, resistance or capacitancecomponents peculiar to high frequency analog circuits, includingmatching and bias circuits. Thus, the high frequencytransmission/reception circuit 100 is large-sized in its entirety toprove hindrance to reduction in size and weight of the communicationterminal equipment.

[0009] In communication terminal equipment, a high frequencytransmission/reception circuit 110 by a direct conversion system,adapted for transmitting/receiving information signals withoutconversion to the intermediate frequency, as shown in FIG. 2, is alsoemployed. In the high frequency transmission/reception circuit 110, theinformation signals, received by an antenna unit 111, are supplied via atransmission/reception switching unit 112 to a demodulating circuit unit113 for direct baseband processing. In the high frequencytransmission/reception circuit 110, information signals generated in asource are directly modulated in a modulating circuit unit 114, withoutconversion to an intermediate frequency, so as to be transmitted from anantenna unit 111 through an amplifier 115 and the transmission/receptionswitching unit 112.

[0010] In the above-described high frequency transmission/receptioncircuit 110, in which information signals are transmitted/received bydirect detection without converting the information signals intointermediate frequency signals, the number of component parts, such asfilters, may be reduced to simplify the overall structure to achieve astructure close to one chip. However, the high frequencytransmission/reception circuit 100 needs to be matched to filters ormatching circuits arranged on the downstream side. In the high frequencytransmission/reception circuit 110, since the signals are amplified at atime in a high frequency stage, it becomes difficult to achieve asufficient gain, so that the amplifying operation needs to be performedin the baseband unit. Thus, the high frequency transmission/receptioncircuit 110 is in need of a circuit for canceling DC offset, orredundant low-pass filters, thus further increasing the overall powerconsumption.

[0011] The conventional high frequency transmission/reception circuit isnot of sufficient characteristics to satisfy required specifications,such as reduction in size or weight of the communication terminalequipment, whether the circuit is of the superheterodyne type or thedirect conversion type. Thus, in the high frequencytransmission/reception circuit, various attempts are being made fordesigning the circuit as a module with a small size by a simplifiedstructure based on for example an Si-CMOS circuit. One of such attemptsis to form passive devices of optimum characteristics on an Si substrateand to build a filter circuit or a resonator on an LSI (large-scaleintegrated circuit) and to integrate a logic LSI of the baseband sectionin an IC to produce a so-called one-chip high frequency substrate.

[0012] In this one-chip high frequency circuit substrate, it is crucialhow to form an inductor unit 120 of high performance, as shown in FIGS.3A and 3B. In this high frequency circuit substrate, a large recess 124is formed in register with an inductor unit forming portion. 123 of anSi substrate 121 and an SiO₂ insulating layer 122. In this highfrequency circuit substrate, a first wiring layer 125 is formed facing arecess 124, while a second wiring layer 126 is formed on the SiO₂insulating layer 122 to form a coil section 127. In the high frequencycircuit substrate, a wiring pattern may, alternatively, be lifted fromthe substrate surface in air to form the inductor unit 120.

[0013] This high frequency circuit substrate suffers a problem that theinductor unit 120 has to be formed by numerous cumbersome process steps,thus raising the cost. Moreover, in the high frequency circuitsubstrate, the electrical interference between the high frequencycircuit section of the analog circuit and the baseband circuit sectionof the digital circuit poses a serious problem.

[0014] As a high frequency circuit substrate, a high frequency circuitsubstrate 130, employing an Si substrate, shown for example in FIG. 4,or a high frequency circuit substrate 140, employing a glass substrate,shown in FIG. 5, has been proposed.

[0015] The high frequency circuit substrate 130, shown in FIG. 4, isarranged so that, with the use of an Si substrate as the base substrate131, an SiO₂ layer 132 is formed on this base substrate 131, and apassive device layer 133 is formed by for example a photolithographictechnique. Although not shown, a passive device unit 135, such as aninductor unit, a resistance unit or a capacitor unit, is formed inmultiple layers, along with a wiring layer 134, through an insulatinglayer 136, in the inside of the passive device layer 133 of the highfrequency circuit substrate 130, in a manner not shown in detail.

[0016] In the high frequency circuit substrate 130, a terminal section137, connected to the wiring layer 134, is formed through e.g., avia-hole on the passive device layer 133. On this terminal section 137,there are mounted functional devices 138, such as high frequency ICs orLSIs, by for example a flip chip mounting method. With the highfrequency circuit substrate 130, the high frequency circuit section isseparated from the baseband circuit section, by mounting on e.g., amotherboard, for preventing electrical interference between the twocircuits.

[0017] Meanwhile, if, with the high frequency circuit substrate 130, thepassive device unit 135 is to be formed within the passive device layer133, the base substrate 131, which is an electrically conductive Sisubstrate, tends to interfere with optimum high frequencycharacteristics of the passive device unit 135.

[0018] On the other hand, in a high frequency circuit substrate 140,shown in FIG. 5, a glass substrate is used as the base substrate 141, inorder to overcome the problem of the base substrate 131 in the highfrequency circuit substrate 130 described above. A passive device layer142 is formed by for example a photolithographic technique on the basesubstrate 141 of the high frequency circuit substrate 140. Although notshown, a passive device unit 144, such as an inductor unit, a resistanceunit or a capacitor unit, is formed in multiple layers, along with awiring layer 143, through an insulating layer 145, in the inside of thepassive device layer 142 of the high frequency circuit substrate 140, ina manner not shown in detail.

[0019] In the high frequency circuit substrate 140, a terminal section146, connected to the wiring layer 143, is formed through e.g., avia-hole on the passive device layer 142. On this terminal section 146,there are directly mounted functional devices 147, such as highfrequency ICs or LSIs, by for example a flip chip mounting method. Inthis high frequency circuit substrate 140, an electricallynon-conductive glass substrate is used as the base substrate 141 tosuppress the capacitive coupling between the base substrate 141 and thepassive device layer 142 to form the passive device unit 144 of optimumhigh frequency characteristics within the passive device layer 142. Inthis high frequency circuit substrate 140, a terminal pattern is formedon the surface of the passive device layer 142, for mounting on e.g., amotherboard, and connection to the motherboard is made by for example awire bonding method.

[0020] In these high frequency circuit substrates 130, 140,high-precision passive device layers 133, 142 are formed on the basesubstrates 131, 141, as described above. In forming the passive devicelayer as a thin film, the base substrates 131, 141 need to exhibitthermal resistance against rise in the surface temperature duringsputtering and contact alignment properties during masking, and to holddepth of focus during the lithographic processing.

[0021] Thus, the base substrates 131, 141 are required to be flat withhigh precision and to exhibit insulating properties, thermal resistanceor resistance against chemicals. The base substrates 131, 141, formed asSi or glass substrate, exhibits these properties, thus enablingformation of an inexpensive low loss passive device by a separateprocess from the LSI forming process.

[0022] In the high frequency circuit substrates 130, 140, passivedevices may be formed to a higher precision on the base substrates 131,141 than is possible with the pattern forming methods by printing asused in the conventional ceramic module technique or with the wetetching methods used for forming a wiring pattern on the printing wiringboard. Additionally, the device size can be reduced to approximately onehundredth of the area of the base substrate. Moreover, with the highfrequency circuit substrates 130, 140, in which an Si substrate or aglass substrate is used as the base substrates 131, 141, the use limitfrequency of the passive device may be increased to 20 GHz or higher.

[0023] In these high frequency circuit substrates 130, 140, patterns forhigh frequency signals, interconnections for supplying the power orproviding ground connection or interconnection for control signals maybeachieved through the wiring layers 134, 143 formed on the basesubstrates 131, 141 described above. Thus, in the high frequency circuitsubstrates 130, 140, such problems may be produced as electricalinterference across respective wirings, increased cost due tomulti-layered wirings or bulkiness in size due to layout of theinterconnections.

[0024] In the high frequency circuit substrates 130, 140, the cost israised further due to use of a relatively expensive Si or glasssubstrate for the base substrates 131, 141.

[0025] In the high frequency circuit substrates 130, 140, the surfacesof the insulating layers 136, 145 become irregular due to thicknesses ofthe subjacent wiring layers 134, 143 to render it difficult to form thewiring layers 134, 143 or via-holes to a high accuracy on the surfacesof these irregular surfaces of the insulating layers 136, 145. In thehigh frequency circuit substrates 130, 140, since the surfaces of theinsulating layers 136, 145 are irregular patterning images of the wiringlayers 134, 143, the patterning images of the wiring layers 134, 143 orthe via-holes become de-focused when the wiring layers 134, 143 or thevias are formed in the insulating layers 136, 145 using a photosensitivematerial, to render it difficult to form the wiring layers 134, 143 orthe via-holes with high precision.

[0026] The high frequency circuit substrates 130, 140 are formed bymounting high frequency module unit 150 on a motherboard 151, asdescribed above, as shown in FIG. 6. Here, the high frequency circuitsubstrate 130 is taken as an example.

[0027] In the high frequency module unit 150, the high frequency circuitsubstrate 130 is mounted on a major surface of the motherboard 151, asshown in FIG. 6. Moreover, the high frequency module unit 150 is sealedin its entirety by a shield cover 152 of, for example, an insulatingresin. In the high frequency module unit 150, the patterninterconnections and input/output terminal units are formed on the frontand back sides of the motherboard 151, while a large number of lands 153are formed around the loading area for the high frequency circuitsubstrate 130.

[0028] In the high frequency module unit 150, the high frequency circuitsubstrate 130 is mounted on the motherboard 151 and, in this state, thewiring layer 136 of this high frequency circuit substrate 130 and thelands 153 are interconnected with wires 154 of the wire bonding methodto supply the power or signals to the high frequency circuit substrate130. Meanwhile, the high frequency circuit substrate 140 is mounted insimilar manner to the motherboard 151.

[0029] In this high frequency module unit 150, including the shieldcover 152 for sealing the functional devices 138, such as high frequencyICs or LSIs, loaded on the high frequency circuit substrate 130, it is afrequent occurrence that heat evolved from the functional devices 138 isconfined in the shield cover 152 to deteriorate the operatingcharacteristics.

[0030] In the high frequency module unit 150, in which the basesubstrate 131 of the high frequency circuit substrate 130 is an Sisubstrate, it is difficult to provide a heat dissipating structure tothe base substrate 131. Moreover, since the passive device layer 133 isprovided through the base substrate 131 on the motherboard 151, thedevice becomes bulky in size along its thickness.

[0031] Moreover, in the high frequency module unit 150, it is difficultto provide a wiring structure in the base substrate 131 of the highfrequency circuit substrate 130 and hence a large number of the lands153 are provided therearound for supplying the power, with theconsequence that the device is increased in size in the planardirection.

DISCLOSURE OF THE INVENTION

[0032] It is therefore an object of the present invention to provide ahigh frequency circuit block unit, a producing method therefor, a highfrequency module device and a producing method therefor, by means ofwhich the problems inherent in the conventional high frequency moduledevice may be overcome.

[0033] It is another object of the present invention to provide a highfrequency circuit block unit, a producing method therefor, a highfrequency module device and a producing method therefor, by means ofwhich passive devices or the wiring unit can be formed with highprecision and the unit or device may be reduced in size and cost.

[0034] The present invention provides a high frequency circuit blockunit comprising a plurality of unit wiring layers, in each of which awiring layer having a passive device and a connection land unit in aportion thereof is formed embedded in a major surface of an insulatinglayer. The plural unit wiring layers are layered on a release layerformed on a major surface of a dummy substrate. The wiring layers of theplural unit wiring layers are electrically interconnected, while themajor surfaces of the plural unit wiring layers are planarized in theirentirety. The dummy substrate and the release layer are removed onpeeling off from the release layer to form the high frequency circuitblock unit.

[0035] In this high frequency circuit block unit, the major surfaces ofthe plural unit wiring layers are planarized in their entirety, and thedummy substrate is removed to produce the block unit. Thus, the majorsurfaces of the respective unit wiring layers are not susceptible tomicro-irregularities, so that the passive devices and the wiring layersmay be formed on the respective unit wiring layers with high precision.Since the base substrate is unneeded, the block unit may be reduced insize and cost.

[0036] The present invention also provides a method for producing a highfrequency circuit block unit comprising a release layer forming step offorming a release layer on a dummy substrate, and a layering step oflayering a plurality of unit wiring layers on the release layer. Each ofthe unit wiring layers includes a wiring layer formed embedded in themajor surface of an insulating layer. The wiring layer includes apassive device and a connection land unit in a portion thereof, whilethe wiring layers of the unit wiring layers are electricallyinterconnected. The method also includes a planarizing step ofplanarizing the major surfaces of the plural unit wiring layers in theirentirety, and a substrate removing step of peeling off the plural unitwiring layers from the release layer for removing the dummy substrateand the release layer.

[0037] In this method for producing a high frequency circuit block unit,plural unit wiring layers, each made up by an insulating layer and awiring layer, are formed on a dummy substrate, the major surfaces of therespective unit wiring layers are planarized in their entirety and thedummy substrate is removed from the plural unit wiring layers to producethe high frequency circuit block unit. Thus, in the present method forproducing a high frequency circuit block unit, the major surfaces of therespective unit wiring layers are not susceptible tomicro-irregularities, so that the passive devices and the wiring layersmay be formed on the respective unit wiring layers with high precision.Since the base substrate is unneeded, the block unit produced may bereduced in size and cost.

[0038] The present invention also provides a high frequency moduledevice comprising a high frequency circuit block unit produced bylayering a plurality of unit wiring layers, in each of which a wiringlayer having a passive device and a connection land unit in a portionthereof is formed embedded in the major surface of an insulating layer,on a release layer formed on a major surface of a dummy substrate. Thewiring layers of the plural unit wiring layers are electricallyinterconnected, while the major surfaces of the plural unit wiringlayers being planarized in their entirety. The dummy substrate and therelease layer are removed to form the high frequency circuit block unit.The high frequency module device also comprises a motherboard having aconnecting portion exposed from a major surface thereof. The highfrequency circuit block unit is mounted to the major surface of themotherboard as the connection land unit and the connecting portion areelectrically interconnected.

[0039] In this high frequency module device, the major surfaces of theplural unit wiring layers, making up the high frequency circuit blockunit, layered on the dummy substrate, are planarized in their entirety,and the dummy substrate is removed to produce the high frequency circuitblock unit. Thus, in the high frequency module device, the majorsurfaces of the respective unit wiring layers of the high frequencycircuit block unit are not susceptible to micro-irregularities, so thatthe passive devices and the wiring layers may be formed on therespective unit wiring layers with high precision. Since the basesubstrate is unneeded, the block unit produced may be reduced in sizeand cost.

[0040] The present invention also provides a method for producing a highfrequency module device comprising a block unit forming step of forminga high frequency block unit, in which the block unit forming stepincludes a release layer forming step of forming a release layer on adummy substrate, a layering step of layering a plurality of unit wiringlayers on the release layer, each of the unit wiring layers including awiring layer formed embedded in the major surface of an insulatinglayer, the wiring layer including a passive device and a connection landunit in a portion thereof, the wiring layers of the unit wiring layersbeing electrically interconnected, a planarizing step of planarizing themajor surfaces of the plural unit wiring layers in their entirety, asubstrate removing step of peeling off the plural unit wiring layersfrom the release layer for removing the dummy substrate and the releaselayer, and a block unit mounting step of mounting the high frequencycircuit block unit on a major surface of a motherboard, having aconnecting portion exposed from a major surface thereof, as theconnecting land unit and the connecting portion are electricallyinterconnected.

[0041] In this producing method for a high frequency module device, aplural number of unit wiring layers, each made up by an insulating layerand a wiring layer, are formed on a dummy substrate, the major surfacesof the unit wiring layers are planarized, and the dummy substrate isremoved from the plural unit wiring layers to form a high frequencycircuit block unit, which is mounted on the motherboard to produce thehigh re module device. Thus, with the present producing method for ahigh frequency module device, the major surfaces of the respective unitwiring layers of the high frequency circuit block unit are notsusceptible to micro-irregularities, so that the passive devices and thewiring layers may be formed on the respective unit wiring layers withhigh precision. Since the base substrate is unneeded, the block unitproduced may be reduced in size and cost.

[0042] Other objects, features and advantages of the present inventionwill become more apparent from reading the embodiments of the presentinvention as shown in the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0043]FIG. 1 is a block circuit diagram showing a high frequencytransmission/reception circuit by a superheterodyne system.

[0044]FIG. 2 is a block circuit diagram showing a high frequencytransmission/reception circuit by a direct conversion system.

[0045]FIG. 3A is a perspective view showing essential portions of aninductor unit provided to a conventional high frequency circuitsubstrate, and FIG. 3B is a longitudinal cross-sectional view thereof.

[0046]FIG. 4 is a longitudinal cross-sectional view showing a structurein which a silicon substrate is used as a base substrate of the highfrequency circuit substrate.

[0047]FIG. 5 is a longitudinal cross-sectional view showing a structurein which a glass substrate is used as a base substrate of the highfrequency circuit substrate.

[0048]FIG. 6 is a longitudinal cross-sectional view showing a highfrequency module device in which the high frequency circuit substratehas been mounted on the motherboard.

[0049]FIG. 7 is a cross-sectional view showing an instance of a highfrequency module device according to the present invention.

[0050]FIG. 8 illustrates a manufacturing process for a high frequencymodule device and specifically depicts a longitudinal cross-sectionalview of a dummy substrate.

[0051]FIG. 9 illustrates a manufacturing process for a high frequencymodule device and specifically depicts a longitudinal cross-sectionalview showing the state in which a first insulating layer has been formedon the dummy substrate.

[0052]FIG. 10 illustrates a manufacturing process for a high frequencymodule device and specifically depicts a longitudinal cross-sectionalview showing the state in which a first wiring groove has been formed inthe first insulating layer.

[0053]FIG. 11 illustrates the manufacturing process for a high frequencymodule device and specifically depicts a longitudinal cross-sectionalview showing the state in which a metal plating layer has been formed ona first insulating layer.

[0054]FIG. 12 illustrates the manufacturing process for a high frequencymodule device and specifically depicts a longitudinal cross-sectionalview showing the state in which a first unit wiring layer has beenformed.

[0055]FIG. 13 illustrates the manufacturing process for a high frequencymodule device and specifically depicts a longitudinal cross-sectionalview showing the state in which a receiving electrode unit has beenformed on a first unit wiring layer.

[0056]FIG. 14 illustrates the manufacturing process for a high frequencymodule device and specifically depicts a longitudinal cross-sectionalview showing the state in which a passive device unit has been formed ona first unit wiring layer.

[0057]FIG. 15 illustrates a manufacturing process for a high frequencymodule device and specifically depicts a longitudinal cross-sectionalview showing the state in which a second unit wiring layer has beenformed on the first unit wiring layer.

[0058]FIG. 16 illustrates a manufacturing process for a high frequencymodule device and depicts a longitudinal cross-sectional view showingthe state in which a passive device unit has been formed on a secondunit wiring layer.

[0059]FIG. 17 illustrates a manufacturing process for a high frequencymodule device and depicts a longitudinal cross-sectional view showingthe state in which a third insulating layer has been formed on thesecond unit wiring layer.

[0060]FIG. 18 illustrates a manufacturing process for a high frequencymodule device and depicts a longitudinal cross-sectional view showingthe state in which a mask has been formed on the third insulating layer.

[0061]FIG. 19 illustrates a manufacturing process for a high frequencymodule device and depicts a longitudinal cross-sectional view showingthe state in which a metal film has been formed on the third insulatinglayer.

[0062]FIG. 20 illustrates a manufacturing process for a high frequencymodule device and depicts a longitudinal cross-sectional view showingthe state in which a third unit wiring layer has been formed on a secondunit wiring layer.

[0063]FIG. 21 illustrates a manufacturing process for a high frequencymodule device and depicts a longitudinal cross-sectional view showingthe state in which a resist layer has been formed on the third unitwiring layer.

[0064]FIG. 22 illustrates a manufacturing process for a high frequencymodule device and depicts a longitudinal cross-sectional view showingthe state in which a functional device has been formed on the third unitwiring layer.

[0065]FIG. 23 illustrates a manufacturing process for a high frequencymodule device and depicts a longitudinal cross-sectional view showingthe state in which a resin layer has been formed on the third unitwiring layer.

[0066]FIG. 24 illustrates a manufacturing process for a high frequencymodule device and depicts a longitudinal cross-sectional view showingthe state in which polishing processing has been applied to thefunctional device and to the resin layer.

[0067]FIG. 25 illustrates a manufacturing process for a high frequencymodule device and depicts a longitudinal cross-sectional view showingthe state in which a dummy substrate has been bonded to a major surfaceof a high frequency block unit.

[0068]FIG. 26 illustrates a manufacturing process for a high frequencymodule device and depicts a longitudinal cross-sectional view showingthe state in which the dummy substrate has been removed from the othermajor surface of the high frequency block unit.

[0069]FIG. 27 illustrates a manufacturing process for a high frequencymodule device and depicts a longitudinal cross-sectional view showingthe state in which bumps have been formed on the other major surface ofthe high frequency block unit.

[0070]FIG. 28 illustrates a manufacturing process for a high frequencymodule device and depicts a longitudinal cross-sectional view showingthe state in which the dummy substrate has been removed from one majorsurface of the high frequency block unit.

[0071]FIG. 29 illustrates a manufacturing process for a high frequencymodule device and depicts a longitudinal cross-sectional view showingthe state in which the high frequency block unit has been mounted on themotherboard.

[0072]FIG. 30is a longitudinal cross-sectional view showing the state inwhich a shield cover and a thermally conductive resin material have beenmounted on the high frequency module substrate.

[0073]FIG. 31 is a longitudinal cross-sectional view showing the statein which a cooling via has been formed in the interior of a motherboardin the high frequency module substrate.

[0074]FIG. 32 is a longitudinal cross-sectional view showing the statein which a metal core is provided in the interior of the motherboard inthe high frequency module device.

BEST MODE FOR CARRYING OUT THE INVENTION

[0075] Referring to the drawings, certain preferred embodiments of thepresent invention will be explained in detail.

[0076] A high frequency module device 1 according to the presentinvention forms a high frequency circuit for performing exchangeoperations, etc. for high frequency signals by, for example, asuperheterodyne system or a direct conversion system, in atransmission/reception unit provided in e.g., a portable communicationterminal equipment, as shown in FIG. 7. The high frequency module device1 is comprised of a high frequency circuit block unit 2, hereinafterreferred to as a block unit, that is a high frequency circuit substrate,electrically connected and mounted to a motherboard 3 by for examplebump units 4, such as solder.

[0077] The block unit 2 includes a second unit wiring layer 6, layeredon the major surface of a first unit wiring layer 5, and a third unitwiring layer 7 on the major surface of the second unit wiring layer 6.These first to third unit wiring layers 5 to 7 are each formed by aninsulating layer and pattern interconnections.

[0078] In the block unit 2, the first unit wiring layer 5 to the thirdunit wiring layer 7 are electrically interconnected by a via 8 extendingthrough the totality of the layers or through the upper and lowerlayers. In the block unit 2, the major surfaces of the first unit wiringlayer 5 to the third unit wiring layer 7 are planarized by achemical-mechanical polishing (CMP) to enable a via-on-via structure inwhich, for example, a via 8 of the second unit wiring layer 6 is formedon a via 8 formed in the first unit wiring layer 5. Since the majorsurfaces of the first unit wiring layer 5 to the third unit wiring layer7 in the block unit 2 are planarized, the pattern interconnections onthe upper layers of the unit wiring layers may be formed with highprecision.

[0079] The block unit 2 is mounted on the major surface of the thirdunit wiring layer 7 in such a manner that functional devices 9, such assemiconductor chips or LSI (large-scale integrated circuit) chips, areelectrically connected to a pattern interconnection of the third unitwiring layer 7 with a bump 10 for a device by for example a flip chipbonding method. The block unit 2 is reduced in its entirety in thicknessby forming a resin layer 11 around the functional devices 9 on the majorsurface of the third unit wiring layer 7 and by polishing thesefunctional devices 9 and the resin layer 11.

[0080] In preset positions in the pattern interconnections in the firstunit wiring layer 5 to the third unit wiring layer 7 of the block unit2, there are formed passive device units, such as a capacitor unit 12, aresistor unit 13 and an inductor unit 14. The capacitor unit 12 is e.g.,a decoupling capacitor or a DC-cut capacitor and is formed as a thinfilm by a tantalum oxide (TaO) film. The resistor unit 13 is e.g., aresistor for a terminal resistor and is formed as a thin film oftantalum nitride (TaN).

[0081] Since the major surfaces of the first unit wiring layer 5 to thethird unit wiring layer 7 of the block unit 2 are planarized, asdescribed above, the passive device units can be formed with highaccuracy. With the block unit 2, in which the passive device units areformed as thin films in each unit wiring layer with high accuracy,without employing e.g., semiconductor chips, passive device units ofsmall size and high performance can be loaded.

[0082] The block unit 2 is formed by sequentially layering the firstunit wiring layer 5 to the third unit wiring layer 7, on a dummysubstrate 30 having a planar major surface, via a release layer 31, withthe first unit wiring layer 5 to the third unit wiring layer 7 beingpeeled off at the release layer 21. Thus, the block unit 2 is of such astructure which does not use a base substrate, such as a glass substrateor an Si substrate. Meanwhile, the dummy substrate 30 may be re-used asnecessary.

[0083] The motherboard 3 is composed of plural wiring layers 15, withthe interposition of insulating layers 16 between the respectiveneighboring layers, with these wiring layers 15 being interconnectedlayer by layer by a via-hole 17 extending through the totality of thewiring layers or through the upper and lower wiring layers. A pluralnumber of input/output terminal units 18 are provided on the front andrear major surfaces of the motherboard 3 and operate as connectionterminals for the external power supply or as a base for the bumps 4 inmounting the block ull it 2. In the motherboard 3, the plural wiringlayers 15 operate as wirings for transmitting e.g., the power, suppliedfrom the input/output terminal units 18, control signals or highfrequency signals to the block unit 2, while also operating as agrounding unit (grounding electrode) 19.

[0084] As a material for the insulating layer 16, in the motherboard 3,such a material low in the dielectric constant and in Tanδ, that issuperior in high frequency characteristics, for example, polyphenyleneether (PPE) bismaleidotriazine (BT-resin), polytetrafluoroethylene,polyimide, liquid crystal polymer (LCP), polynorbornene (PNB), phenolicresin or polyolefin resin, as organic materials, ceramics, as inorganicmaterials, or glass-epoxy, as a mixture of organic and inorganicmaterials, is used. It is noted that the motherboard 3 is manufacturedthrough a routine multi-layered wiring substrate manufacturing process.

[0085] The method for manufacturing the above-described high frequencymodule device 1 is now explained. For producing the high frequencymodule device 1, a block unit 2 is first prepared. For forming the blockunit 2, the dummy substrate 30 having the release layer 31 on its majorsurface 30 a is prepared. As the dummy substrate 30, such a substrateexhibiting high thermal resistance and having highly planarized majorsurface, such as a glass substrate, a quartz substrate or an Sisubstrate, is used. The release layer 31 is formed by a metal film 31 aof metal, such as copper or aluminum, formed to an even thickness on theorder of 1000 Åover the entire surface of the major surface 30 a of thedummy substrate 30 by e.g., a sputtering method or a chemical vapordeposition method (CVD), and a resin film 31 b of, for example,polyimide resin, formed to a thickness on the order of 1 to 2 μm on theentire surface of the metal film 31 a by e.g., a spin coating method.

[0086] Then, a first insulating layer 32 is formed to an even thicknesson the release layer 31, as shown in FIG. 9. The first insulating layer32 is formed as a film from an insulating dielectric material, generallyknown in the conventional wiring substrate manufacturing process. Forthe first insulating layer 32, an insulating dielectric material low indielectric constant and in Tanδ, that is superior in high frequencycharacteristics, such as polyphenylene ether (PPE) bismaleidotriazine(BT-resin), liquid crystal polymer (LCP), polynorbornene (PNB),polyimide, benzocyclobutene (BCB), epoxy resin or acrylic resin, isused. The first insulating layer 32 is formed as a film, by coating theinsulating dielectric material, on the release layer 31, by for examplethe spin coating method, curtain coating method, roll coating method ordip coating method.

[0087] Then, in the first insulating layer 32, an opening 32 a, which isto become the via 8, is formed by patterning at a predeterminedposition. The opening 32 a is formed by patterning the first insulatinglayer 32. If the photosensitive insulating dielectric material is usedas the first insulating layer 32, the opening 32 a is formed bypatterning by the photolithographic technique. If a non-photosensitiveinsulating dielectric material is used as the first insulating layer 32,the opening 32 a is patterned by dry etching or laser processing, usinga mask of aluminum or a photoresist.

[0088] The first insulating layer 32 is then etched to form first wiringgrooves 33, as shown in FIG. 10. The first wiring grooves 33 are formedby forming an etching mask, having openings corresponding to the patternof the first wiring grooves 33, on the first insulating layer 32,applying dry etching to an area of the first insulating layer 32 notcovered by the etching mask, by a reactive ion etching (RIE) by forexample an oxygen plasma, and by removing the etching mask.

[0089] A metal plating layer 34 then is formed by metal platingprocessing on the first insulating layer 32, already provided with thefirst wiring grooves 33, as shown in FIG. 11. The metal plating layer 34is formed of a highly electrically conductive metal, such as copper. Formetal plating processing, any of electrolytic plating or electrolessplating may be used. The metal plating is so performed that the metalplating layer 34 is applied to the entire major surface of the firstinsulating layer 32 provided with the first wiring grooves 33 and intothe openings 32 a so that the thickest portion of the metal platinglayer 34 is thicker than the thickest portion of the first insulatinglayer 32. During the metal plating processing, in which the metalplating layer 34 is formed by the electrolytic plating, a metal film 31a of the release layer 31 operates as the voltage applying electrode.

[0090] The metal plating layer 34 is then processed with planarizing,until the first insulating layer 32 is exposed, to form a first patternwiring 35 on the main surface of the first insulating layer 32, as shownin FIG. 12. This forms a first unit wiring layer 5, made up by the firstinsulating layer 32 and the first pattern wiring 35, and having a majorsurface highly planarized by the planarizing processing, referred tobelow as one major surface 5 a, on the release layer 31. Since theplanarizing processing simultaneously polishes the first insulatinglayer 32 and the metal plating layer 34, formed of different materials,the chemical-mechanical polishing (CMP) method is used. This CMP methodallows polishing with material selectivity, such as to increase thepolishing rate of the metal plating layer 34 of metal, such as copper,and allows the surface being polished to be planarized with highaccuracy.

[0091] If, in this first unit wiring layer 5, a photosensitiveinsulating dielectric material is used for the first insulating layer32, the first insulating layer 32 is formed on the highly planarizedmajor surface 30 a of the dummy substrate 30 and hence suffers from novariations in thickness, defocusing of the patterning image by thephotolithographic processing may be suppressed to enable the formationof the first pattern wiring 35 or the via 8 with high accuracy.

[0092] In the first unit wiring layer 5, thus formed, the first patternwiring 35 is embedded in the first insulating layer 32, while the onesurface 5 a is highly planarized by the planarizing processing by theCMP method. The vias 8 are also formed simultaneously. Since the ends ofthe vias 8 exposed to the one major surface 5 a of the first unit wiringlayer 5 are similarly highly planarized, the electrical connection ofthe first unit wiring layer 5 to the second unit wiring layer 6, formedabove the first unit wiring layer 5 by a process as later explained, maybe of a via-on-via structure in which the electrical connection is bythe vias 8. This via-on-via structure enables electrical connectionacross the respective unit wiring layers by the shortest path, whileallowing surface area reduction of the block unit 2.

[0093] On the one major surface 5 a of the first unit wiring layer 5 arethen formed, as passive devices, a lower electrode of the capacitor unit1.2 and a receiving electrode unit 36 as a receiving electrode of theresistor unit 13, as shown in FIG. 13. In forming the receivingelectrode unit 36, a first metal film of a metal, such as titanium, isformed on the entire surface of the one major surface 5 a of the firstunit wiring layer 5 having the vias 8, by for example a sputteringmethod or a vapor deposition method, to a thickness on the order of 200Å. A second metal film of, for example, Cu, Al, Au or Pt, is formed to athickness on the order of 2000 Å on the entire metal film surface.

[0094] A mask then is formed on a region of the major surface of thesecond metal film, in which to form the receiving electrode unit 36, andetching is applied to a non-masked area. This etching is by wet etchingwith the use of an acid mixture, obtained on mixing e.g., nitric acid,sulfuric acid or acetic acid, in a preset ratio, as an etchant. Sincethe etchant composed of the acid mixture attacks metal titanium only toa lesser extent, only the non-masked second metal film is attacked, ifthe etching is continued until the first metal film is exposed.

[0095] Then, etching is applied to the non-masked first metal film. Thisetching is by wet etching, using an acid mixture, obtained on mixinge.g., ammonium hydrofluorate and ammonium monohydrogen difluoride, in apredetermined ratio, as an etchant, or by plasma etching by e.g., CF₄plasma. With this etching, only the first metal film can be etched,because the etchant or the CF₄ plasma attacks metals other than metaltitanium only to a lesser extent. This forms the receiving electrodeunit 36, made up by the first and second metal films, on the first unitwiring layer 5.

[0096] The capacitor unit 12 and the resistor unit 13 are then formed,as passive device units, so as to be connected to the receivingelectrode unit 36, as shown in FIG. 14. When forming these passivedevice units, a tantalum nitride (TaN) film is formed on the entirety ofthe one major surface 5 a of the first unit wiring layer 5 for overlyingthe receiving electrode unit 36. This TaN film is a base film for thedielectric film of tantalum oxide (TaO) which is to become the capacitor12 on anodic oxidation. In forming this TaN film, a sputtering method,capable of forming a film to a thickness of the order of e.g., 2000 Å,may preferably be used.

[0097] A mask for anodic oxidation only of the portion of the TaN layerwhere the capacitor unit 12 and the resistor unit 13 are formed is thenformed on the TaN layer. This anodically oxidizes the portion of the TaNlayer which is exposed to outside of the mask opening. The portion ofthe TaN layer exposed to outside from the mask opening is then processedwith anodic oxidation. In this processing of anodic oxidation, a voltageof 50 to 200V is applied in an electrolytic solution of, for example,ammonium borate, so that TaN will operate as an anode, thereby oxidizingthe TaN layer to form the TaO layer. Meanwhile, the TaO layer may beformed to a desired thickness by adjusting the voltage applied to theTaN layer.

[0098] The mask formed on the anodically oxidized TaN layer is thenremoved. By so doing, the TaO layer, obtained on selective oxidation ofthe surface of the TaN layer, may become the dielectric material of thecapacitor unit 12. The TaO layer then is dry-etched, as the site of theTaO layer, on which the capacitor unit 12 and the resistor unit 13 areto be formed, is masked with a resist. By removing the mask, thecapacitor unit 12 and a dielectric film 37 of the resistor unit 13 areformed simultaneously. By so doing, passive device units, such as thecapacitor unit 12 and the resistor unit 13, are formed on the first unitwiring layer 5. Since these passive device units are formed on the onemajor surface 5 a of the highly planarized first unit wiring layer 5,the passive device units can be formed with high precision to improvehigh frequency characteristics. Meanwhile, the capacitor unit 12 may beformed using e.g., a BST (Ba, Sr, Ti, 0) film or an STO (Sr, Ti, 0) filmas the dielectric film 37.

[0099] An upper electrode unit 38 is then formed on the capacitor unit12. This upper electrode unit 38 is a film of metals, such as Al, Cu, Ptor Au, formed via an underlying layer, designed for improving thebonding, such as a film of Cr, Ni or Ti. When Al or Cu is used as theupper electrode unit 38, the upper electrode unit 38 is formed on thefirst unit wiring layer 5 so as to overlie the passive device units,such as by sputtering, to a thickness of the order of 2000 Å. The upperelectrode unit is then formed to a preset pattern such as by masking andetching.

[0100] On the first unit wiring layer 5, the second unit wiring layer 6is then formed to overlie the passive device units, formed on the onemajor surface 5 a, as shown in FIG. 15. This second unit wiring layer 6is formed using the material and the process similar to those for thefirst unit wiring layer. The second unit wiring layer 6 is formed by asecond insulating layer 39 and a second pattern wiring 40. If thephotosensitive dielectric material is used for the second insulatinglayer 39 in the second unit wiring layer 6, the second insulating layer39 is formed on the highly planarized first unit wiring layer 5 and isnot subjected to thickness variations. Thus, it becomes possible toprevent defocusing of the patterning image by the photolithographicprocessing to form the second pattern wiring 40 and the via 8 wiht highaccuracy.

[0101] Since the second unit wiring layer 6 is formed on the one majorsurface 5 a of the highly planarized first unit wiring layer 5, thesecond pattern wiring 40 may be formed with high accuracy. A majorsurface 6 a of the second unit wiring layer 6 facing the pattern wiring40, hereinafter referred to as the one major surface 6 a, has alreadybeen put to planarizing processing by the aforementioned CMP method andis planarized with high precision similarly to the one major surface 5 aof the first unit wiring layer 5. In the block unit 2, the unit wiringlayers are of a three-layered structure. This is not limitative andthree or more unit wiring layers may also be provided by repeating theprocess of forming the first unit wiring layer 5.

[0102] On the one major surface 6 a of the second unit wiring layer 6,there is formed a capacitor unit 41, as a passive device unit, as shownin FIG. 16. This capacitor unit 41 is formed by a forming processsimilar to that of the capacitor unit 12 formed on the one major surface5 a of the first unit wiring layer 5. The capacitor unit 41 is formed onthe one major surface 6 a of the second unit wiring layer 6 and hence isformed with high precision to improve high frequency characteristics.

[0103] On the one major surface 6 a of the second unit wiring layer 6,there is formed the film of the aforementioned insulating dielectricmaterial, as a third insulating layer 42. This third insulating layer 42is formed of a material similar to the material of the first unit wiringlayer 5 and the second unit wiring layer 6. The third insulating layer42 is formed to cover the capacitor unit 41 formed on the one majorsurface 6 a of the second unit wiring layer 6. This third insulatinglayer 42 is formed on the highly planarized one major surface 6 a of thesecond unit wiring layer 6, and hence has a surface 42 a planarized withhigh precision.

[0104] A plural number of via-holes 43 are then formed in the thirdinsulating layer 42. These via-holes 43 are formed in association withthe upper electrode unit 41 a and the second pattern wiring 40, formedon the capacitor unit 41, for partially exposing an upper electrode unit46 and the pattern wiring 40. It is noted that, if the photosensitiveinsulating dielectric material is used as the third insulating layer 42,it is possible to suppress the defocusing of the patterning image by thephotolithographic processing. Thus, the via-holes 43 may be formed withhigh accuracy.

[0105] In the third insulating layer 42, a mask 44 then is formed bypatterning, to a thickness on the order of 12 μm, for opening apredetermined location of the third insulating layer, by for example thephotolithographic technique, as shown in FIG. 18. It is noted that themask 44 may also be formed by any other suitable method, instead of bythe photolithographic technique, with the use of any suitable material.

[0106] On the third insulating layer 42, now provided with the mask 44,there is formed a metal film 45 to a thickness on the order of 10 μm, byfor example a plating method, as shown in FIG. 19. This metal film 45 isformed by metal, such as copper.

[0107] This mask 44 then is removed from the third insulating layer 42,as shown in FIG. 20. In this manner, a third pattern wiring 46, with athickness on the order of 10 μm, is formed on the third insulating layer42. In a portion of this third pattern wiring 46, there is formed aninductor 14 by patterning. In this inductor 14, a series resistancevalue presents a problem. Since the third pattern wiring 46 is formed toa sufficient thickness by e.g., a plating method, a sufficient functionmay be achieved even at a low frequency, thus allowing suppression ofthe loss in inductor characteristics. In this manner, the third unitwiring layer 7, made up by the third insulating layer 42 and the thirdpattern wiring 46, is formed on the second unit wiring layer 6.

[0108] A resist layer 47 is then formed on the third unit wiring layer 7for covering the entire major surface thereof, as shown in FIG. 21. Forthis resist layer 47, a solder resist or an insulating dielectricmaterial, for example, is used. The resist layer 47 then is subjected toa photolithographic processing, through a mask patterned to apredetermined shape, to form an opening 47 a, exposed to the thirdpattern wiring 46, at a predetermined position. The portion of the thirdpattern wiring 46, exposed from the opening 47 a, is subjected toelectroless plating of nickel/copper to form a basis unit 48 for thebump 10 for a device.

[0109] The functional device 9, such as a semiconductor chip or an LSIchip, then is mounted on top of the third unit wiring layer 7, as shownin FIG. 22. This functional device 9 is electrically connected 10 thebasis unit 48, formed on the third unit wiring layer 7, via the bump 10for a device, by the flip chip bonding method. Meanwhile, the mountingmethod for the functional device 9 is not limited to the flip chipbonding method, such that a face-down mounting method, for example, atape automated bonding (TAB) method or the reed beam bonding method, mayalso be used.

[0110] On the third unit wiring layer 7, a resin layer 11 is then formedto overlie the mounted functional device 9, as shown in FIG. 23. Theresin layer 11 is formed on the entire major surface of the third unitwiring layer 7, by, for example, a transfer molding method or by aprinting method, so that the resin will be charged even into a spacebetween the functional device 9 and the third unit wiring layer 7. Forthe resin layer 11, such a resin having only a low rate of shrinkage dueto thermosetting, such as epoxy resin, is used. By so doing, it ispossible in the first unit wiring layer 5 to third unit wiring layer 7to prevent deformation, such as warping, due to contraction at the timeof thermosetting of the resin layer 11.

[0111] The functional device 9 and the resin layer 11 are subjected topolishing, as shown in FIG. 24. This polishing processing is carried outby a mechanical polishing method employing a grinder, a chemicalpolishing method by wet etching, or a method employing these methods incombination (CMP method). The functional device 9 is polished, alongwith the resin layer 11, up to a limit thickness not obstructing theoperation. This polishing proceeds in such a manner that the perimeteralong the direction of the polishing surface of the functional device 9is charged with the resin layer 11, using the dummy substrate 30 as asupporting substrate for the functional device 9 and the resin layer 11,so that no step difference will be produced between the functionaldevice 9 and the resin layer 11. It is therefore possible to preventedge defects of the functional devices 9 from being produced. The blockunit 2, made up by the first unit wiring layer 5 to the third unitwiring layer 7 and which is provided with the functional device 9 andthe resin layer 11, is formed as described above.

[0112] On a polished surface, hereinafter referred to as a major surface2 a, of the functional devices 9 and the resin layer 11 of the blockunit 2, a dummy substrate 49 is bonded through a release layer 48, asshown in FIG. 25. The release layer 48 is formed of the same material asthe release layer 31, is of the same structure and produced by the sameprocess as the release layer 31. The release layer 48 is made up bymetal film 48 a and resin film 48 b. Similarly to the dummy substrate 30described above, the dummy substrate 49 is formed by a glass substrate,a quartz substrate or an Si substrate exhibiting high thermal resistanceand which has a highly planarized major surface.

[0113] The dummy substrate 30 then is removed from the block unit 2along with the release layer 31, as shown in FIG. 26. Specifically, thedummy substrate 30 and the release layer 31 are dipped, along with theblock unit 2, in an acidic solution of, for example, hydrochloric acidor nitric acid, so that the acidic solution is intruded into a spacebetween the metal film 31 a and the resin film 31 b, as the acidicsolution slightly dissolves the metal film 31 a of the release layer 31.The dummy substrate 30 is removed as the peel-off proceeds between themetal film 31 a and the resin film 31 b, with the resin film 31 b beingleft over on a surface 2 b of the first unit wiring layer 5 of the blockunit 2, hereinafter referred to as the other major surface.Consequently, a protective layer, for example, may be formed at theoutset on the other major surface 2 b of the block unit 2. The dummysubstrate 30 may also be removed by for example laser ablation from theblock unit 2.

[0114] The resin film 31 b, formed on the other major surface 2 b of theblock unit 2, is removed by for example a dry etching method by anoxygen plasma. This exposes the via 8 on the other major surface 2 b ofthe block unit 2. Since the major surface of the dummy substrate 30,facing the block unit 2, is highly planarized, the other major surface 2b of the block unit 2 is also highly planarized.

[0115] The bump 4 by e.g., a solder is formed on the via 8 exposed onthe other major surface 2 b of the block unit 2, as shown in FIG. 27.The bump 4, operating as an electrical connecting unit in mounting theblock unit 2 on the motherboard 3, may be formed as a nickel/copperplating layer by for example electrolytic plating or electrolessplating. The block unit 2, having the dummy substrate 49 as a supportingsubstrate, is free of flexure, so that the bump 4 may be formedaccurately on the other major surface 2 b.

[0116] The dummy substrate 49 then is removed from the block unit 2along with the release layer 48, as shown in FIG. 28. The dummysubstrate 49 and the release layer 48 are removed from the one majorsurface 2 a of the block unit 2 in the same way as when removing thedummy substrate 30 and the release layer 31 from the other major surface2 b of the block unit 2.

[0117] The block unit 2 then is mounted on the motherboard 3, with theother major surface 2 b as a mounting surface, along with the othersemiconductor chip 50, as shown in FIG. 29. The motherboard 3 includes aplural number of wiring layers 15, each having a grounding section 19therein, and includes an input/output terminal unit 18 exposed from aprotective layer 51, formed by e.g., a resist, on its major surface 3 a,hereinafter referred to as a mounting surface, on which the block unit2, etc., is mounted.

[0118] The block unit 2 is mounted on the motherboard 3 by beingelectrically connected via bump 4 to the input/output terminal unit 18exposed from the mounting surface 3 a of the motherboard 3.Specifically, an under-fill 52 is charged into a space between themotherboard 3 and the block unit 2, with the bump unit 4 facing theinput/output terminal unit 18, and the resulting assembly is heated infor example a solder reflow vessel for electrically connecting theinput/output terminal unit 18 and the bump unit 4 for mounting the blockunit 2 on the mounting surface 3 a of the motherboard 3. This completesthe high frequency module device 1 formed by the block unit 2 and themotherboard 3.

[0119] In this high frequency module device 1, the block unit 2 isformed by sequentially layering the first unit wiring layer 5 to thirdunit wiring layer 7 on the dummy substrate 30 and by releasing the dummysubstrate 30. The one major surface 5 a of the first unit wiring layer 5and the one major surface 0.6 a of the second unit wiring layer 6 areplanarized with high precision by the CMP method.

[0120] Thus, with the present high frequency module device 1, in whichmicro-irregularities may be prohibited from being formed on the onemajor surface 5 a of the first unit wiring layer 5 and on the one majorsurface 6 a of the second unit wiring layer 6, and the pattern wirings,vias and the passive device units may be formed with high precision, itis possible to improve high frequency characteristics as well as toachieve a higher density and a smaller area of the wiring. With thishigh frequency module device 1, since the block unit 2 is not in need ofthe base substrate, it is possible to reduce the size along thethickness and to lower the cost.

[0121] With the present high frequency module device 1, in which pluralwiring layers 15, operating as wirings or grounding sections 19 fortransmitting the power, control signals or the high frequency signals tothe block unit 2, are provided within the motherboard 3, there is nonecessity of providing a land for supplying the power to the vicinity ofthe block unit 2 on, for example, the mounting surface 3 a of themotherboard 3, and in which the block unit 2 can be mounted directlyabove the input/output terminal unit 18, it is possible to reduce thearea of the device.

[0122] With the present high frequency module device 1, in which thewiring layers 15 and the grounding sections 19 having a sufficient areaare formed on the motherboard 3, it is possible to supply the power ofhigh regulation to the block unit 2.

[0123] Moreover, with the present high frequency module device 1, ashield cover 53 for eliminating the effect of the electromagnetic noiseis assembled to overlie the block unit 2 and the semiconductor chip 50mounted via input/output terminal unit 18 on the mounting surface 3 a ofthe motherboard 3, as described above, as shown in FIG. 30.

[0124] Thus, in the high frequency module device 1, in which the blockunit 2 and the semiconductor chip 50 are covered by the shield cover 53,it is a frequent occurrence that the heat evolved from the functionaldevices 9 or the semiconductor chip 50 in the block unit 2 on themounting surface 3 a of the motherboard 3 be confined in the shieldcover 53 to affect high frequency characteristics. Thus it is preferredto provide the high frequency module device 1 with a suitable heatradiating structure.

[0125] Thus, in the high frequency module device 1, a heat conductiveresin material 54 is charged into a space between the one major surface2 a of the block unit 2 and the shield cover 53 to form the heatradiating structure. In the high frequency module device 1, the heatevolved from the functional devices 9 of the block unit 2 may betransmitted through the heat conductive resin material 54 to the shieldcover 53, this shield cover 53 operating as a heat radiating section toprevent the heat from being confined in the inside of the shield cover53 to affect the high frequency characteristics. Meanwhile, in the highfrequency module device 1, the block unit 2 is held by the heatconductive resin material 54 and the shield cover 53 to improve themechanical mounting toughness.

[0126] In a high frequency module device 60, shown in FIG. 31, the heatevolved from the block unit 2 and the semiconductor chip 50 is designedto be radiated more efficiently. In addition to the heat conductiveresin material 54, numerous cooling vias 61, communicating with theinside of the motherboard 3, are formed in register with the loadingregion of the block unit 2. These cooling vias 61 are formed by aprocess similar to the process used for forming the via-holes 17 in themotherboard 3.

[0127] In the high frequency module device 60, the heat evolved from thefunctional devices 9 of the block unit 2 is radiated from the shieldcover 53 through the heat conductive resin material 54, while beingtransmitted to the bottom surface of the motherboard 3 through thecooling vias 61 so as to be radiated to outside. In the high frequencymodule device 60, efficient heat radiation is achieved by heat radiationfrom the block unit 2 and the motherboard 3. Meanwhile, the heatradiating structure for the high frequency module device 60 may beformed solely by the cooling vias 61. With the high frequency moduledevice 60, the wiring layer 62 provided on for example the motherboard 3may be of an increased thickness of, for example, 50 nm, with thecooling vias 61 being connected to the wiring layer 62 for effectingheat radiation from the wiring layer 62.

[0128] In a high frequency module device 70, shown in FIG. 32, a metalcore 71 of a metal having high electrical conductivity, such as copperor copper alloys, is provided within the motherboard 3. In the highfrequency module device 70, the aforementioned numerous cooling vias 61are connected to this metal core 71. In the high frequency module device70, heat may be radiated from the metal core 71 through the cooling vias61. By the structure of the heat conductive resin material 54 and thecooling vias 61, more efficient heat radiation may be achieved toimprove the reliability.

[0129] The present invention is not limited to the above-describedembodiments and, as may be apparent to those skilled in the art, variouschanges, substitutions or equivalents may be envisaged without departingfrom the scope and the purport of the invention as defined in theappended claims.

INDUSTRIAL APPLICABILITY

[0130] According to the present invention, the high frequency moduledevice is manufactured by layering a plural number of unit wiringlayers, each formed by an insulating layer and a wiring layer,planarizing the major surfaces of the respective unit wiring layers intheir entirety, by peeling off the plural unit wiring layers from thedummy substrate to form a high frequency circuit block unit and bymounting the so produced high frequency circuit block unit on themotherboard.

[0131] Thus, according to the present invention such a high frequencymodule device may be produced in which micro-irregularities may beprevented from being formed on the major surfaces of the respective unitwiring layers of the high frequency circuit block unit, the passivedevices or the wiring sections layered on the respective unit wiringlayers may be formed to high accuracy and in which the high frequencycircuit block unit obtained on layering on a dummy substrate and thenpeeling off the dummy substrate is mounted on the motherboard in a statenot in need of a base substrate, thereby achieving reduction is size andcost.

[0132] According to the present invention, the wiring section or thegrounding section for transmitting the power, control signals or thehigh frequency signals to the high frequency circuit block unit isprovided within the interior of the motherboard, while the highfrequency circuit block unit is not in need of the base substrate, thehigh frequency circuit block unit may be mounted directly above theconnection section of the motherboard, thus allowing area reduction ofthe high frequency module device.

1. A high frequency circuit block unit comprising: a plurality of unitwiring layers, in each of which a wiring layer having a passive deviceand a connection land unit in a portion thereof is formed embedded in amajor surface of an insulating layer; said plural unit wiring layersbeing layered on a release layer formed on a major surface of a dummysubstrate; said wiring layers of said plural unit wiring layers beingelectrically interconnected; the major surfaces of said plural unitwiring layers being planarized in their entirety; said dummy substrateand said release layer being removed on peeling off from said releaselayer to form the high frequency circuit block unit.
 2. The highfrequency circuit block unit according to claim 1 wherein the majorsurfaces of said plural unit wiring layers have been planarized bychemical mechanical polishing.
 3. The high frequency circuit block unitaccording to claim 1 wherein said plural unit wiring layers include, onthe major surface neighboring to said release layer and/or on the majorsurface of the uppermost layer above said release layer, a semiconductorchip and a resin layer which covers said semiconductor chip so that saidsemiconductor chip is partially exposed.
 4. The high frequency circuitblock unit according to claim 3 wherein said semiconductor chip and theresin layer have been polished.
 5. A method for producing a highfrequency circuit block unit comprising: a release layer forming step offorming a release layer on a dummy substrate; a layering step oflayering a plurality of unit wiring layers on said release layer so thatwiring layers of said unit wiring layers, each including a passivedevice and a connection land unit in a portion thereof, and each formedembedded in the major surface of an insulating layer, are electricallyinterconnected; a planarizing step of planarizing the major surfaces ofsaid plural unit wiring layers in their entirety; and a substrateremoving step of peeling off said plural unit wiring layers from saidrelease layer for removing said dummy substrate and the release layer.6. The method for producing the high frequency circuit block unitaccording to claim 5 wherein, in said planarizing step, the majorsurface of each of said plural unit wiring layers is planarized bychemical-mechanical polishing.
 7. The method for producing a highfrequency circuit block unit according to claim 5 further comprising,subsequent to said substrate removing step, a semiconductor chipmounting step of mounting a semiconductor chip on the major surface ofsaid plural unit wiring layers neighboring to said release layer and/oron the major surface of the uppermost layer above said release layer, aresin layer forming step of forming a resin layer for covering saidsemiconductor chip so that said semiconductor chip is partially exposed,and a polishing step of polishing said semiconductor chip and said resinlayer.
 8. A high frequency module device comprising: a high frequencycircuit block unit produced by layering a plurality of unit wiringlayers, in each of which a wiring layer having a passive device and aconnection land unit in a portion thereof is formed embedded in themajor surface of an insulating layer, on a release layer formed on amajor surface of a dummy substrate; said wiring layers of said pluralunit wiring layers being electrically interconnected, the major surfacesof said plural unit wiring layers being planarized in their entirety,said dummy substrate and said release layer being removed on peeling offfrom the release layer to form the high frequency circuit block unit,and a motherboard having a connecting portion exposed from a majorsurface thereof; said high frequency circuit block unit being mounted tothe major surface of said motherboard as said connection land unit andsaid connecting portion are electrically interconnected.
 9. The highfrequency module device according to claim 8 wherein the major surfacesof plural unit wiring layers in said high frequency circuit block unithave been planarized by chemical-mechanical polishing.
 10. The highfrequency module device according to claim 8 wherein said high frequencycircuit block unit includes, on a major surface thereof neighboring tosaid release layer and/or on an opposite side major surface thereofopposite to said major surface, a semiconductor chip and a resin layercovering said semiconductor chip so that said semiconductor chip ispartially exposed.
 11. The high frequency module device according toclaim 10 wherein said semiconductor chip and the resin layer have beenpolished.
 12. A method for producing a high frequency module devicecomprising: a block unit forming step of forming a high frequency blockunit by a release layer forming step of forming a release layer on adummy substrate, a layering step of layering a plurality of unit wiringlayers on said release layer, each of said unit wiring layers includinga wiring layer formed embedded in the major surface of an insulatinglayer, said wiring layer including a passive device and a connectionland unit in a portion thereof, said wiring layers of said unit wiringlayers being electrically interconnected, a planarizing step ofplanarizing the major surfaces of said plural unit wiring layers intheir entirety, and a substrate removing step of peeling off said pluralunit wiring layers from said release layer for removing said dummysubstrate and the release layer, and a block unit mounting step ofmounting said high frequency circuit block unit on a major surface of amotherboard, having a connecting portion exposed from a major surfacethereof, as said connecting land unit and said connecting portion areelectrically interconnected.
 13. The method for producing a highfrequency module device according to claim 12 wherein, in saidplanarizing step of said block unit forming step, the major surfaces ofsaid plural unit wiring layers are each planarized bychemical-mechanical polishing.
 14. The method for producing a highfrequency module device according to claim 12 wherein, in said blockunit forming step, said high frequency circuit block unit is formed byexecuting, subsequent to said substrate removing step, a semiconductorchip mounting step of mounting a semiconductor chip on the major surfaceof said plural unit wiring layers neighboring to said release layerand/or on the major surface of the uppermost layer above said releaselayer, a resin layer forming step of forming a resin layer for coveringsaid semiconductor chip so that said semiconductor layer is partiallyexposed, and a polishing step of polishing said semiconductor chip andsaid resin layer.